The M-PSK Demodulator Baseband block demodulates a signal that was modulated using the M-ary phase shift keying method. The input is a baseband representation of the modulated signal. The input and output for this block are discrete-time signals. This block accepts a scalar-valued or column vector input signal. For information about the data types each block port supports, see Supported Data Types.
The M-ary number parameter, M, is the number of points in the signal constellation.
When you set the Output type parameter to Integer, the block outputs integer values between 0 and M-1. M represents the M-ary number block parameter.
When you set the Output type parameter to Bit, the block outputs binary-valued signals that represent integers. The block represents each integer using a group of K = log2(M) bits, where K represents the number of bits per symbol. The output vector length must be an integer multiple of K.
Depending on the demodulation scheme, the Constellation ordering or Symbol set ordering parameter indicates how the block maps a symbol to a group of K output bits. When you set the parameter to Binary, the block maps the integer, I, to [u(1) u(2) ... u(K)] bits, where the individual u(1) are given by
u(1) is the most significant bit.
For example, if M = 8, Constellation ordering (or Symbol set ordering) is set to Binary, and the integer symbol value is 6, then the binary input word is [1 1 0].
When you set Constellation ordering (or Symbol set ordering) to Gray, the block assigns binary outputs from points of a predefined Gray-coded signal constellation. The predefined M-ary Gray-coded signal constellation assigns the binary representation
to the Mth phase. The zeroth phase in the constellation is the Phase offset parameter, and successive phases are counted in a counterclockwise direction.
Note This transformation might seem counterintuitive because it constitutes a Gray-to-binary mapping. However, the block must use it to impose a Gray ordering on the signal constellation, which has a natural binary ordering.
In other words, if the block input is the natural binary representation, u, of the integer U, the block output has phase
jθ + j2πm/M
where θ is the Phase offset parameter and m is an integer between 0 and M-1 that satisfies
For example, if M = 8, the binary representations that correspond to the zeroth through seventh phases are as follows.
M = 8; m = [0:M-1]'; de2bi(bitxor(m,floor(m/2)), log2(M),'left-msb') ans = 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 1 1 0 0
The following diagram shows the 8-ary Gray-coded constellation that the block uses if the Phase offset parameter is .
For M=2, refer to the BPSK Demodulator Baseband block reference page.
For M=4, refer to the QPSK Demodulator Baseband block reference page.
For M=8 and greater, see the following signal diagrams.
Hard-Decision 8-PSK Demodulator Floating-Point Signal Diagram
Hard-Decision 8-PSK Demodulator Fixed-Point Signal Diagram
Hard-Decision M-PSK Demodulator (M > 8) Floating-Point Signal Diagram for Nontrivial Phase Offset
For M > 8, in order to improve speed and implementation costs, no derotation arithmetic is performed when Phase offset is 0, , , or (i.e., when it is trivial).
Also, for M > 8, this block will only support inputs of type double and single.
The number of points in the signal constellation.
The phase of the zeroth point of the signal constellation.
Determines how the block maps a symbol to the corresponding K output bits or integer. See the reference page for the M-PSK Modulator Baseband block for details. Selecting User-defined displays the field Constellation mapping, allowing for user-specified mapping.
This field appears when User-defined is selected in the drop-down list Constellation ordering.
This parameter is a row or column vector of size M and must have unique integer values in the range [0, M-1]. The values must be of data type double.
The first element of this vector corresponds to the constellation point at 0 + Phase offset angle, with subsequent elements running counterclockwise. The last element corresponds to the -2π/M + Phase offset constellation point.
Determines whether the output consists of integers or groups of bits. If this parameter is set to Bit, the M-ary number parameter must be 2K for some positive integer K.
Specifies the output to be bitwise hard decision, LLR, or approximate LLR. This parameter appears when you select Bit from the Output type drop-down list. The output values for Log-likelihood ratio and Approximate log-likelihood ratio decision types are of the same data type as the input values
This field appears when Approximate log-likelihood ratio or Log-likelihood ratio is selected for Decision type.
When set to Dialog, the noise variance can be specified in the Noise variance field. When set to Port, a port appears on the block through which the noise variance can be input.
This parameter appears when the Noise variance source is set to Dialog and specifies the noise variance in the input signal. This parameter is tunable in normal mode, Accelerator mode and Rapid Accelerator mode.
If you use theSimulink® Coder™ rapid simulation (RSIM) target to build an RSIM executable, then you can tune the parameter without recompiling the model. This is useful for Monte Carlo simulations in which you run the simulation multiple times (perhaps on multiple computers) with different amounts of noise.
The LLR algorithm involves computing exponentials of very large or very small numbers using finite precision arithmetic and would yield:
Inf to -Inf if Noise variance is very high
NaN if Noise variance and signal power are both very small
In such cases, use approximate LLR, as its algorithm does not involve computing exponentials.
Data Types Pane for Hard-Decision
For bit outputs, when Decision type is set to Hard decision, the output data type can be set to 'Inherit via internal rule', 'Smallest unsigned integer', double, single, int8, uint8, int16, uint16, int32, uint32, or boolean.
For integer outputs, the output data type can be set to 'Inherit via internal rule', 'Smallest unsigned integer', double, single, int8, uint8, int16, uint16, int32, or uint32.
When this parameter is set to 'Inherit via internal rule' (default setting), the block will inherit the output data type from the input port. The output data type will be the same as the input data type if the input is a floating-point type (single or double). If the input data type is fixed-point (supported only when M-ary number is 2, 4, or 8), the output data type will work as if this parameter is set to 'Smallest unsigned integer'.
When this parameter is set to 'Smallest unsigned integer', the output data type is selected based on the settings used in the Hardware Implementation pane of the Configuration Parameters dialog box of the model.
If ASIC/FPGA is selected in the Hardware Implementation pane, and Output type is Bit, the output data type is the ideal minimum one-bit size, i.e., ufix(1). For all other selections, it is an unsigned integer with the smallest available word length large enough to fit one bit, usually corresponding to the size of a char (e.g., uint8).
If ASIC/FPGA is selected in the Hardware Implementation pane, and Output type is Integer, the output data type is the ideal minimum integer size, i.e., ufix(ceil(log2(M))). For all other selections, it is an unsigned integer with the smallest available word length large enough to fit the ideal minimum size, usually corresponding to the size of a char (e.g., uint8).
This parameter only applies when M-ary number is 2, 4, or 8, the input is fixed-point, and Phase offset is nontrivial. The phase offset is trivial when:
You set M-ary number to 2 and Phase offset to a multiple of
You set M-ary number to 4 and Phase offset to an even multiple of
When you set M-ary number to 8 there are no trivial phase offsets.
Data Types Pane for Soft-Decision
For bit outputs, when Decision type is set to Log-likelihood ratio or Approximate log-likelihood ratio, the output data type is inherited from the input (e.g., if the input is of data type double, the output is also of data type double).
|Port||Supported Data Types|
This block supports HDL code generation using HDL Coder™. HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic. For more information on implementations, properties, and restrictions for HDL code generation, see M-PSK Demodulator Baseband in the HDL Coder documentation.