Implement serial-in, parallel-out shift register
Control and Measurements/Additional Components
The Discrete Shift Register block outputs a vector containing the last N samples of the input signal. When the input contains more than one signal, the block outputs the last N samples of each signal in the following order:
Out = [u1(k), u1(k−1), u1(k−2), u1(k−3), u2(k), u2(k−1), u2(k−2), u2(k−3)]
This example shows the block output for an input containing two signals, represented by u1 and u2, and a number of samples N = 4, represented by the k to k−3 indices. The dimension of the output vector is 4 × 2 = 8.
Specify the number of samples, or stages, of the register. The minimum value is 1.
Specify the initial value of the N-1 samples preceding time 0. Enter a scalar value or a vector of the same size as the input signal.
Specify the time interval between the samples.
|Scalar Expansion||Yes, of the parameter Initial inputs|