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Master/Slave Synchronization with GE® Fanuc PCI-5565 Boards

This example shows how to synchronize and communicate between two target computers over shared/reflective memory using GE® Fanuc PCI-5565 boards. Both the PCI-5565PIORC and the (formerly VMIC) VMIPCI-5565 boards are supported. The master target computer runs the model vmicIntDemoMaster and uses the '5565 broadcast' block to generate the interrupt that clocks the slave target computer. The slave computer runs the model vmicIntDemoSlave and syncs to the shared memory interrupt. The slave's interrupt source is set to GE_Fanuc(VMIC)_PCI-5565 under the model configuration parameters Simulink Real-Time options section.

The MATLAB® script, vmicIntDemoPartDef.m, constructs the node and partition read/write buffers. This script is executed in the PreLoadFcn callback of each model found under File --> Model Properties.

Open, Build, and Download the Master Model to TargetPC1

Open the master model vmicIntDemoMastervmicIntDemoMaster. Under the model configuration parameters Simulink Real-Time options section, verify that the following settings are specified:

  • System target file: slrt.tlc

  • Specify target PC name: TargetPC1

  • Name of Simulink Real-Time object created by build process: tgM

Building the model creats the application vmicIntDemoMaster.dlm, which is downloaded to TargetPC1.

% Open the model.
mdlOpen = 0;
systems = find_system('type', 'block_diagram');
if ~any(strcmp('vmicIntDemoMaster', systems))
  mdlOpen = 1;
  open_system('vmicIntDemoMaster');
end

Build the model and download to the master target computer, TargetPC1.

set_param('vmicIntDemoMaster','RTWVerbose','off'); % Configure for a non-Verbose build.
rtwbuild('vmicIntDemoMaster');                     % Build and download application.

% Close the model if we opened it.
if (mdlOpen)
  bdclose('vmicIntDemoMaster');
end
### Starting Simulink Real-Time build procedure for model: vmicIntDemoMaster
### Generated code for 'vmicIntDemoMaster' is up to date because no structural, parameter or code replacement library changes were found.
### Successful completion of build procedure for model: vmicIntDemoMaster
### Looking for target: TargetPC1
### Download model onto target: TargetPC1

Open, Build, and Download the Slave Model to TargetPC2

Open the slave model vmicIntDemoSlavevmicIntDemoSlave. Under the model configuration parameters Simulink Real-Time options section, verify that the following settings are specified:

  • System target file: slrt.tlc

  • Specify target PC name: TargetPC2

  • Name of Simulink Real-Time object created by build process: tgS

  • Real-time interrupt source: Auto (PCI only)

  • I/O board generating the interrupt: GE_Fanuc(VMIC)_PCI-5565

  • PCI slot: -1

If you installed more than one 5565 board in TargetPC2, you must specify the PCI slot data, [bus, slot], for the board you wish to use. Using autosearch, -1, may select the wrong board.

Building the model creates the application, vmicIntDemoSlave.dlm, which is downloaded to TargetPC2.

% Open the model.
mdlOpen = 0;
systems = find_system('type', 'block_diagram');
if ~any(strcmp('vmicIntDemoSlave', systems))
  mdlOpen = 1;
  open_system('vmicIntDemoSlave');
end

Build the model and download to the slave target computer, TargetPC2.

set_param('vmicIntDemoSlave','RTWVerbose','off'); % Configure for a non-Verbose build.
rtwbuild('vmicIntDemoSlave');                     % Build and download application.

% Close the model if we opened it.
if (mdlOpen)
  bdclose('vmicIntDemoSlave');
end
### Starting Simulink Real-Time build procedure for model: vmicIntDemoSlave
### Generated code for 'vmicIntDemoSlave' is up to date because no structural, parameter or code replacement library changes were found.
### Successful completion of build procedure for model: vmicIntDemoSlave
### Looking for target: TargetPC2
### Download model onto target: TargetPC2

Run both Models

Using the Simulink Real-Time object variables tgM and tgS, start the models.

start(tgS);                              % Start slave model.
start(tgM);                              % Start master model.
pause(5);                                % Let the models run for at least 5 sec.

Display the Master Target Computer Scopes

Capture and display the video screen on the master target computer. This is the data sent to the slave target computer via shared memory.

tgM.viewTargetScreen
Warning: The EraseMode property will be removed in a future release. 

Display the Slave Target Computer Scopes

Capture and display the video screen on the slave target computer. This is the data received from the master target computer via shared memory. Notice that the simulation execution time is the same as (synchronized to) the Master Clock.

tgS.viewTargetScreen
Warning: The EraseMode property will be removed in a future release. 

Stop both Models

When done, stop both model applications.

stop(tgS);
stop(tgM);

% EOF vmicIntDemo.m
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