Virtual Overlay Metrology for Fault Detection with Machine Learning
Emil Schmitt-Weaver, ASML
To build up the structures that make up a microchip, some as small as 5nm, a silicon wafer moves though a lithography apparatus multiple times. This puts increased emphasis on reducing the influence known contributors have toward the on-product overlay budget. Using MATLAB® and Simulink®, ASML applied a machine learning technique known as function approximation to gain insight to how known contributors, such as those collected with scanner metrology, influence the on-product overlay budget. The result is a sufficiently trained function that can approximate overlay for all wafers exposed with the lithography system.
Recorded: 28 Jun 2016
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