Version 2.4, part of Release 2017b, includes the following enhancements:

  • Code Optimization for Reusable Subsystems: Generate more efficient code for reusable subsystems
  • Function Block Instance Naming: Control naming by using instance names of reusable subsystems
  • Named Constant Inlining: Control handling of named constants in generated code
  • MATLAB Function Block Variable Reuse Control: Improve readability of the generated code Release details

See the Release Notes for details.

Version 2.3, part of Release 2017a, includes the following enhancements:

  • Code Optimization for Initialization Code: Optimize generated code by removing redundant timer initialization calls
  • rand Function Support: Generate code for rand functions on PLC IDEs that support uint32
  • Syntax Highlighting in Code Generation Report: Read generated code more easily with syntax highlighting
  • Code Optimization for Unused Stateflow Events: Generate more efficient code for unused events

See the Release Notes for details.

Version 2.2, part of Release 2016b, includes the following enhancements:

  • Ladder Logic Support: Generate ladder diagrams from Stateflow charts for CODESYS 3.5 IDE and Rockwell Automation AOIs
  • Rockwell Automation IDE Support: Generate code for RSLogix 5000 V20 and Studio 5000 Logix Designer V24 IDEs
  • Multirate Support: Generate code from multirate models for Siemens IDEs and Rockwell Automation AOIs
  • Global Variables for Rockwell Automation IDEs: Generate code for global variables by using INOUT variables for Rockwell Automation AOIs

See the Release Notes for details.

Version 2.1, part of Release 2016a, includes the following enhancements:

  • INOUT Variable Support: Generate INOUT variables for MATLAB Function and Truth Table blocks that use the same name for input and output data
  • Alias Data Type Support: Optionally preserve alias names for data types in generated code to help integration with target-specific data types
  • Simulink Requirements Links: Embed requirements links as comments in generated code
  • Simulink Design Verifier Integration: Generate code with multiple test benches from test harness models created with Simulink Design Verifier
  • 64-bit Windows 7 Support for Siemens STEP 7 and RSLogix 5000 IDEs: Generate, import, and verify code for these IDEs

See the Release Notes for details.

Version 2.0, part of Release 2015b, includes the following enhancements:

  • SIEMENS TIA Portal V12 and V13 IDE Support: Generate code for these IDEs
  • Streamlined Target IDE Selection: Choose target IDE more quickly
  • Absolute Time Temporal Logic by Using IEC 61131 Timer: Generate code for this Stateflow construct
  • Global Variables for Siemens IDEs: Generate code for global data store memory using Simulink.Signal objects for Siemens STEP 7 and TIA Portal IDEs
  • Additional Math Function Support: Generate code for hyperbolic functions
  • Code Optimizations: Generate more efficient code for type casts’
  • Linked Subsystems Code Verification: Verify that generated code results match simulation results

See the Release Notes for details.